Semiconductor devices such as memory devices are tested during manufacture by applying pulses to a terminal of a selected memory device while data is being written to or read from the memory device. Ideally, the operation of the memory device during such a test will not be affected by the pulses. The pulses are typically provided from a pulse generator. It is often desirable to program the voltage levels of the pulses with a programmable pulse generator. It is also desirable that the pulses have relatively high voltage levels with a fast rise time and a fast fall time.
One conventional method of generating pulses at programmable voltage levels is to generate a standard logic level pulse from a conventional logic device such as a CMOS gate, a Field Programmable Gate Array (FPGA), or an Application-Specific Integrated Circuit (ASIC). The standard logic level pulse is then converted to a programmable level by an additional circuit such as a pin driver device. Pin driver devices are general purpose devices used in a wide range of applications. However, pin driver devices generally do not have the capability to generate relatively high voltage level pulses which have a fast rise time and a fast fall time.
Programmable pulses may also be generated by a conventional pulse generator 10 shown in FIG. 1. The pulse generator 10 includes three voltage sources 12, 14, and 16. Each of the voltage sources 12, 14, and 16 has an output coupled to an input of a respective one of three electromechanical relays 18, 20, and 22. Each of the electromechanical relays 18, 20, and 22 has an output coupled to an output terminal 24, and it receives a respective control signal from a system logic circuit 26. The system logic circuit 26 generates the control signals to render each of the electromechanical relays 18, 20, and 22 conductive in a sequence to couple the outputs of the voltage sources 12, 14, and 16 to the output terminal 24 in a sequence to generate voltage pulses. The voltage pulses may be applied to a memory device 28 coupled to the output terminal 24.
The electromechanical relays 18, 20, and 22 have a slow reaction time and, as a result, there is a long delay between a change in one of the control signals and a change in the conductive state of the electromechanical relay which receives the control signal. The slow reaction time of the electromechanical relays 18, 20, and 22 slows the operation of the pulse generator 10 with respect to the speed of operation of the memory device under test. The slow operation of the pulse generator 10 adds significant overhead cost to a test of a memory device.